A Novel Design of Low-Power 1-Bit CMOS Full-Adder Cell using XNOR and MUX

INTERNATIONAL JOURNAL OF MANAGEMENT & INFORMATION TECHNOLOGY

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Field Value
 
Title A Novel Design of Low-Power 1-Bit CMOS Full-Adder Cell using XNOR and MUX
 
Creator Lakshmaiah, Dayadi
Subramanyam, Dr. M.V.
Prasad, Dr. K.Sathya
 
Subject Power Delay Product; High and Low threshold voltages; parasitic capacitances; Area
 
Description This paper process a novel design for low power 1-bit CMOS full adder using XNOR and MUX, with reduced number of transistors using GDI cell. The circuits were simulated with supply voltage scaling from 1.2V to 0.6V &0.6V to 0.3V. To achieve the desired performance of power delay product, area, capacitance the transistors with low threshold voltage were used at critical paths and high threshold voltage at non critical paths. The results show the efficiency of the proposed technique in terms of power consumption, delay and area. 
 
Publisher CIRWORLD
 
Date 2012-12-30
 
Type info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
Peer-reviewed Article
 
Format application/pdf
 
Identifier http://cirworld.com/index.php/ijmit/article/view/702
 
Source INTERNATIONAL JOURNAL OF MANAGEMENT & INFORMATION TECHNOLOGY; Vol 7 No 3; 1155-1165
2278-5612
 
Language eng
 
Relation http://cirworld.com/index.php/ijmit/article/view/702/686
 
Rights Copyright (c) 2013 INTERNATIONAL JOURNAL OF MANAGEMENT & INFORMATION TECHNOLOGY
http://creativecommons.org/licenses/by/4.0
 

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