A Cost Effective DVI interface on Virtex-5 FPGA Through Verilog HDL

INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY

View Publication Info
 
 
Field Value
 
Title A Cost Effective DVI interface on Virtex-5 FPGA Through Verilog HDL
 
Creator A S, Asif Ahmad
 
Subject Computing sciences, Electrical Engineering, VLSI, FPGA Image Processing.
Pixefeeder; DVI; pixelcounter; SDR2DDR; I2CDRAM master; FIFO initial; PLL.
 
Description There is a definite need for video and image processing technologies in today's world. However the computer vision technologies need to be tested and optimized. There is need for testing these interfaces for the platform which we work on. This modeling is a cost effective architecture for interfacing Digital Visual Interface(DVI) on Virtex5 FPGA's. The architecture is modeled in such a way that it does not use XPS micro blaze or Power PC  processor but simple pixel feeder design, configuration of the Chrontel 7301C chip design and the interface between them.
 
Publisher CIRWORLD
 
Date 2014-02-02
 
Type info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
Peer-reviewed Article
An experimental approach is used here. The result used here can be used straightaway for other VLSI image processing applications. The Verilog design with each of its coding lines with its relevant diagrams is used here. The lines of code are highlighted
 
Format application/pdf
 
Identifier http://cirworld.com/index.php/ijct/article/view/2905
 
Source INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY; Vol 13 No 2; 4230-4236
2277-3061
 
Language eng
 
Relation http://cirworld.com/index.php/ijct/article/view/2905/2827
 
Rights Copyright (c) 2016 INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY
http://creativecommons.org/licenses/by/4.0
 

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