CENSORSHIP OF LEAKAGE PARAMETERS OF A FINFET BASED SCHMITT TRIGGER AT NANO-METER REGIME

International Journal of Students' Research in Technology & Management

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Field Value
 
Title CENSORSHIP OF LEAKAGE PARAMETERS OF A FINFET BASED SCHMITT TRIGGER AT NANO-METER REGIME
 
Creator Mishra, Vishwas
Kumar, Abhishek
Tyagi, Shobhit
Verma, Neha
Mishra, Divya
 
Subject Schmitt Trigger
Slew Rate
Leakage Power
Average Power
Delay
Schmitt Trigger
 
Description Purpose: Recently FinFET technology has gained a lot of attention because of its superior fabrication process that is very similar to the fabrication of a conventional transistor. FinFETs unique feature as well as the potential applications make it a strong contender for the low power chip designs. Research is in full swing to use FinFET in analog circuits like Schmitt trigger, sensors, OPAMP and digital logic. The realization of the FinFET based circuits predicts that it is possible to broaden the concept of Moore’s law without unstoppable scaling of CMOS devices.
Methodology: This work is carried out on the Candence Simulation tool. After the simulation, all these parameters have been compared with previous published 4T Schmitt trigger at 45nm with this design and found that they are in close vicinity.
Main Findings: By combining the superior flexibility and reduced short channel effects (SCEs) of FinFET devices offers a promising approach to implement highly integrated, power-efficient Schmitt Trigger circuit for low power digital applications. Schmitt trigger is a device capable of removing unwanted noise from the input and prevent the other operations from this unwanted noise and improve the performance of the device.
Implications: This study is discussing and performs a comparative analysis of different leakage parameters of a FinFET based Schmitt Trigger with previous 4T Schmitt Trigger at 45nm.
The novelty of Study: Size, power, speed, Cost etc. are important factors for designing any new circuits in the field of Electronics. Various eminent researchers have been making efforts for this. This paper makes some effort to discuss about past research and design a new circuit where the value of delay, leakage power and dynamic power reduces when compared to previously published circuits.
 
Publisher GIAP Journals
 
Date 2020-06-16
 
Type info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
Peer-reviewed Article
 
Format application/pdf
 
Identifier https://giapjournals.com/ijsrtm/article/view/ijsrtm.2020.821
10.18510/ijsrtm.2020.821
 
Source International Journal of Students' Research in Technology & Management; Vol. 8 No. 2 (2020); 01-05
2321-2543
 
Language eng
 
Relation https://giapjournals.com/ijsrtm/article/view/ijsrtm.2020.821/3051
 
Rights Copyright (c) 2020 Mishra et al.
https://creativecommons.org/licenses/by-sa/4.0
 

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