FPGA Based Implementation of Cascaded Multi-level Inverter with Adjustable DC

International Journal of Research and Engineering

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Title FPGA Based Implementation of Cascaded Multi-level Inverter with Adjustable DC
Creator Firouzkouhi, Hatef
Description In this paper, total harmonic distortion (THD) minimization problem for cascaded H-Bridge multilevel inverters (CHB-MLIs) with unequal DC sources is studied, which the DC voltage levels of CHB-MLI is considered to be dependent on switching angles. Two forms of variations are proposed for DC voltage, considering corresponding switching angles. A simplified THD formulation, independent from the DC voltage is presented. Both Homotopy method and Genetic Algorithm is applied for THD minimization using Selective Harmonic Elimination PWM (SHEPWM). The results show less THD results using GA. The simulation results are demonstrated by experiments on a seven-level inverter controlled by Xilinx SPARTAN3 FPGA (XC3S400-PQG208). The results show that switching angles for minimum THD can be considered constant for desired fundamental voltages.
Publisher IJRE Publisher
Date 2018-08-07
Type info:eu-repo/semantics/article
Peer-reviewed Article
Format application/pdf
Identifier https://digital.ijre.org/index.php/int_j_res_eng/article/view/348
Source International Journal of Research and Engineering; Vol 5 No 7 (2018): July 2018 Edition; 450-456
Language eng
Relation https://digital.ijre.org/index.php/int_j_res_eng/article/view/348/316
Rights Copyright (c) 2018 Hatef Firouzkouhi

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